[CST-2] Comparative Architectures

[Barnaby Gray]

On Thu, May 30, 2002 at 10:32:52PM +0100, Alvin wrote:
> Well, aliasing means that > 1 virtual address points to the same physical
> address.  If the index size < page size, then there's a physical address
> available to every virtual address, which means no aliasing needed.

Hmm.. this doesn't sound quite right to me. I don't think the solution
proposed is to prevent aliasing, it is to prevent the cache storing
two lines for the same physical address.

I think the reason is because if you have a virtual address:
40       34             14         5          2 0
|Ignored | Tag          |  Index   |Line index| |

And this is mapped to a physical address:
|....................|    Page index/offset     |
                     n<---
(where 2^n is the size of pages)

Then if the size of this page index is larger than the index used into
the cache, then when you get aliasing the two aliased addresses will
share a common index into the cache (since they must have the same
page offset into the physical page they both map to) and so you will
never have the problem of two entries existing in the cache for the
same physical address, but with different virtual addresses.

I think that works..

Barnaby