[CST-2] Comparative Architectures Question

[Anthony Jones]

On Fri, May 24, 2002 at 07:03:05PM +0100, Chris North wrote:
> Am just doing some past tripos questions and have a problem with 99/8/4
> 
> In the third bit where it asks how the choice of page size/cache sizes
> will affect the OS virtual memory system.  Which I can't really think of
> anything for.  I know the number of bits required to specify a location in
> the cache is 14 bits (and hencw we would expect a 50bit tag), and I know
> for 8KB pages the offset within the page is specified in 13 bits (Meaning
> the page is specified in 51 bits.  Now I know if we use 50 bits for the
> tag this could mean that we get virtual memory aliases, but why don't we
> just use 51 bits tag???????

IIRC, we *do* use a 51 bit tag, but this doesn't stop aliasing, since the
cache is indexed by virtual address and two different virtual addresses may
map to the same physical address, hence the same bit of memory could be
cached in two different lines of the cache. Essentially, the problem with
aliasing is not making sure that the cache entry is the right one, but
making sure the entry is the only one. The OS needs to pick the virtual
addresses it assigns carefully to avoid this.

HTH,

Ant