[CST-2] Comp. Arch 1998.7.3 - backwards compatibility problems

[Barnaby Gray]

On Sat, Jun 01, 2002 at 10:28:30PM +0100, George wrote:
> "Older computer architectures often contain features that hamper
> high-performance implementation using modern techniques. Describe several
> such features, explaining how they affect implementation; describe what
> techniques (if any) have been developed to help overcome these
> difficulties." [14 marks]
> 
> So far, I have the following:
<snip>
> o    Unaligned memory accesses: loading/storing a register from an address
> that is not a multiple of the word size. Requires two loads, bytemasking,
> ORing and then maybe a store, instead of one load/store. Complicates
> pipeline stages again, increases transistor count, limits clock speed. Can
> also throw exceptions partway through. Overcome by: emulation in u-code, or
> raising exception to OS (!).

One small addition - support for subword loads/stores are a (very)
similar problem, but maybe another point.

Barnaby