[CST-2] OptComp CST99/9/4: Instruction Scheduling

[M.Y.W.Y. Becker]

Hi again,

Thanks everyone for the answers to my last question!

I would like to check whether someone has got an alternative solution or 
additional ideas to 99/9/4 (a) and (b).

My answer is:

(a)
* true: A programmer could use an extra register r1:
 ld.w r0,a
 ld.w r1,c
 st.w r0,b
 st.w r1,d
and thus avoid load delays. [What does the ".w" stand for, actually?]

* automatic register allocation causes more variables to live in the same 
register => interlocs are more likely

* but: * modern processors can do dynamic scheduling
       * manual assembly coding is hardly feasible in most cases



(b)
Some sort of instruction scheduling might be useful even on this machine. 
Consider the program
a:=b+c;
b:=a;
d:=0;
e:=0;
f:=0;
g:=0;

These instructioned would be partitioned into three groups:
Group1: a:=b+c, nop, nop, nop
Group2: b:=a, d:=0, e:=0, f:0
Group3: g:=0, nop, nop, nop

Rescheduling the instructions, we only need two groups:
Group1: a:=b+c, d:=0, e:=0, f:=0
Group2: b:=a, nop, nop, nop


Cheers,
Mo