[Cst-1b] Computer design ARM Thumb

[Ewan Mellor]

On Wed, 31 May 2000, Shu Yan Chan wrote:

> Hi all!
> In page 35 of Computer Design notes, Slide 9-15
> It said: Since IF's occur only 50% of the time, memory operations may
> sometimes interleave efficiently
> 
> What does it really mean?

>From memory: The memory bus is still 32 bits wide, so by having an
instruction set which is 16 bits wide we can get two instructions in one
go.  This means that every other cycle we are not doing an instruction
fetch, so when we access the memory bus (loads/stores), we stall less,
because the bus isn't being used.  When you do a normal store, the
pipeline stalls because we cannot fetch the next instruction at the start
of the pipeline and execute the store at the same time.

Ewan.